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S72NS-N Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBitTM Flash Memory & DRAM 128 Mb (8 M x 16 bit)/256 Mb (16 M x 16 bit), 110nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/Write, Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR DRAM Data Sheet
ADVANCE INFORMATION
Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Publication Number S72NS128_256ND0_00
Revision B
Amendment 1
Issue Date November 9, 2005
Advance
Information
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
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Full Production (No Designation on Document)
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"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S72NS128/256ND0 Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
S72NS-N Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBitTM Flash Memory & DRAM 128/256 Mb (8/16 M x 16 bit), 110nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/Write, Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR DRAM Data Sheet
ADVANCE INFORMATION
General Description
This document contains information on the S72NS-N MCP product family. Refer to the S29NS-N data sheet (S29NS256/128N_01, revision A4) for full electrical specifications of the Flash memory component. Refer to the DDR SDRAM Type 1 data sheet (revision A2) for full electrical specifications of the DDR SDRAM component. Refer to the DDR SDRAM Type 5 data sheet (revision A0) for full electrical specifications of the DDR SDRAM component The S72NS Series is a product line of stacked Multi-Chip Product (MCP) products and consists of: One or more NS family multiplexed Flash memory die DDR DRAM The products covered by this document are listed in the table below.
DRAM Density Flash Density 128 Mb 256 Mb 512 Mb 128 Mb S72NS128ND0 S72NS256ND0 S72NS512ND0 S72NS512NE0 256 Mb S72NS256ND0
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V Burst Speeds -- Flash = 66 MHz, 80 MHz -- DRAM = 133 MHz Packages, 133-ball FBGA -- 11.0 x 10.0 x 1.0 mm -- 8.0 x 8.0 x 1.0 mm Operating Temperature of 25C to +85C
Product Selector Guide
Device- Model# S72NS256ND0-7K S72NS256ND0-7J S72NS256ND0-73 S72NS256ND0-72 S72NS128ND0-1K S72NS128ND0-1J S72NS128ND0-13 S72NS128ND0-12 S72NS512ND0-7K S72NS512ND0-7J S72NS512ND0-73 S72NS512ND0-72 S72NS512NE0-7K S72NS512NE0-7J S72NS512NE0-73 S72NS512NE0-72 512 Mb 256 Mb 512 Mb 128 Mb 128 Mb 128 Mb 256 Mb 128 Mb Flash Density DRAM Density Flash Speed (MHz) 66 80 66 80 66 80 66 80 66 80 66 80 66 80 66 80 133 133 DRAM Speed (MHz) Supplier DRAM Type 1 DRAM Type 5 DRAM Type 1 DRAM Type 5 DRAM Type 1 DRAM Type 5 DRAM Type 1 DRAM Type 5 MTA133 11x10mm Package NLC133, 11x10mm
NLE133, 8x8mm
Publication Number S72NS128_256ND0_00
Revision B
Amendment 1
Issue Date November 9, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Advance
Information
Contents
1 2 MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 256 Mb Flash + 128 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 512 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 512 Mb Flash + 256 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 128 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 NLC133--133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.2 NLE133--133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 MTA133--133-ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 11.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4 5
6
2
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
Advance
Information
1
MCP Block Diagrams
F-RST# F-VPP F-WP# F-CE# F-OE# F-WE# AVD# F-VSS F2-CE#
RST# VPP WP# CE# OE# WE# AVD# VSS
A15-A0 DQ15-DQ0
ADQ15-ADQ0
MUX Flash Memory NS-N
CLK RDY
F-CLK F-RDY
A16-Amax VCC VCCQ
A16-Amax F-VCC F-VCCQ
Second NS-N (if needed)
D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-Amax - D-A0 D-VCC D-VCCQ VCC VCCQ
(Note 3)
RAS# CAS# BA0 BA1 CKE WE#
CLK CLK# DQS0 DQS1 LDQM UDQM TEST DQ15-DQ0 VSS VSSQ
D-CLK D-CLK# D-LDQS D-UDQS D-LDQM D-UDQM D-TEST D-DQ15 - D-DQ0 D-VSS D-VSSQ
DDR DRAM Memory
Notes:
1. 2. 3. Amax indicates highest address bit for memory component: a. Amax = A23 for NS256N, A22 for NS128N b. Amax = A11 for 128 Mb DDR DRAM, A12 for 256-Mb DDR DRAM For Flash, A0 - A15 is tied to DQ0 - DQ15. For the NS512N, two NS-N devices are included. All signals are common to both except for CE#. F-CE# becomes F1-CE#, while the CE# for the second flash is F2-CE#. This way, the two NS-N devices are separately accessed.
Figure 1.1.
MCP Block Diagram
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
3
Advance
Information
2
2.1
Connection Diagrams
256 Mb Flash + 128 Mb DDR SDRAM Pinout
Legend
A1 DNU
A2 D-TEST
A3 D-VSSQ
A4 D-VCCQ
A5 D-DQ9
A6 D-DQ8
A7 D-VSS
A8 D-VCC
A9 D-VCC
A10 D-DQ5
A11 D-DQ3
A12 D-VSSQ
A13 DNU
A14 DNU
Do Not Use
B1 DNU B2 D-VSS B3 D-DQ13 B4 D-UDQS B5 D-DQ10 B6 D-VSSQ B7 D-VCCQ B8 D-VCCQ B9 D-LDQM B10 D-DQ6 B11 D-DQ4 B12 D-DQ1 B13 D-VCCQ B14 DNU
C1 D-VCC
C2 D-DQ15
C3 D-DQ14
C4 D-DQ12
C5 D-DQ11
C6 D-UDQM
C7 D-VSS
C8 D-VCC
C9 D-VSSQ
C10 D-DQ7
C11 D-LDQS
C12 D-DQ2
C13 D-DQ0
C14 D-VSS
Code Flash Only
D1 RFU
D2 NC
D3 NC
D4 INDEX
D12 F-OE#
D13 ADQ8
D14 D-VCC
E1 RFU
E2 A22
E3 A17
E12 ADQ9
E13 ADQ1
E14 ADQ0
DRAM Only
F1 A23
F2 A19
F3 A18
F12 F-VSS
F13 ADQ3
F14 ADQ2
G1
G2
G3
G12
G13
G14
Reserved for Future Use
F-CE#
F-WP#
F-WE#
F-VCCQ
ADQ11
ADQ10
H1
H2
H3
H12
H13
H14
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
No Connect
J1 A16
J2 F-VSS
J3 NC
J12 F-VSS
J13 F-VSS
J14 ADQ5
K1 A21
K2 F-AVD#
K3 NC
K12 NC
K13 ADQ7
K14 ADQ6
Index Location
L1 A20
L2 F-RST#
L3 D-CE#
L12 F-VCCQ
LA13 ADQ15
L14 ADQ14
M1 NC
M2 NC
M3 D-A3
M4 D-A6
M5 D-A9
M6 D-CKE
M7 D-VSS
M8 D-WE#
M9 D-A10
M10 D-A1
M11 RFU
M12 NC
M13 F-RDY
M14 F-VSS
N1 DNU P1 DNU
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14 DNU P14 DNU
D-VSS P2 DNU
D-VCC
D-A5
D-A8
D-CAS#
D-CLK#
D-BA1
D-A11
D-A2
RFU
RFU
F-VCC P13 DNU
P3 NC
P4 D-A4
P5 D-A7
P6 D-RAS#
P7 D-CLK
P8 D-VCC
P9 D-BA0
P10 D-A0
P11 D-VCC
P12 D-VSS
Figure 2.1.
133-ball Fine-Pitch Ball Grid Array, 256 Mb Flash + 128 Mb DDR DRAM
4
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
Advance
Information
2.2
512 Mb Flash + 128 Mb DDR SDRAM Pinout
Legend
A1 DNU
A2 D-TEST
A3 D-VSSQ
A4 D-VCCQ
A5 D-DQ9
A6 D-DQ8
A7 D-VSS
A8 D-VCC
A9 D-VCC
A10 D-DQ5
A11 D-DQ3
A12 D-VSSQ
A13 DNU
A14 DNU
Do Not Use
B1 DNU B2 D-VSS B3 D-DQ13 B4 D-UDQS B5 D-DQ10 B6 D-VSSQ B7 D-VCCQ B8 D-VCCQ B9 D-LDQM B10 D-DQ6 B11 D-DQ4 B12 D-DQ1 B13 D-VCCQ B14 DNU
C1 D-VCC
C2 D-DQ15
C3 D-DQ14
C4 D-DQ12
C5 D-DQ11
C6 D-UDQM
C7 D-VSS
C8 D-VCC
C9 D-VSSQ
C10 D-DQ7
C11 D-LDQS
C12 D-DQ2
C13 D-DQ0
C14 D-VSS
Flash Shared
D1 RFU
D2 NC
D3 NC
D4 INDEX
D12 F-OE#
D13 ADQ8
D14 D-VCC
E1 RFU
E2 A22
E3 A17
E12 ADQ9
E13 ADQ1
E14 ADQ0
Flash 1 Only
F1 A23
F2 A19
F3 A18
F12 F-VSS
F13 ADQ3
F14 ADQ2
Flash 2 Only
G1
G2
G3
G12
G13
G14
F1-CE#
F-WP#
F-WE#
F-VCCQ
ADQ11
ADQ10
H1
H2
H3
H12
H13
H14
DRAM Only
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1 A16
J2 F-VSS
J3 NC
J12 F-VSS
J13 F-VSS
J14 ADQ5
Reserved for Future Use
K1 A21
K2 F-AVD#
K3 NC
K12 NC
K13 ADQ7
K14 ADQ6
L1 A20
L2 F-RST#
L3 D-CE#
L12 F-VCCQ
LA13 ADQ15
L14
No Connect
ADQ14 M1 NC M2 NC M3 D-A3 M4 D-A6 M5 D-A9 M6 D-CKE M7 D-VSS M8 D-WE# M9 D-A10 M10 D-A1 M11 RFU M12 F2-CE# M13 F-RDY M14 F-VSS
N1 DNU P1 DNU
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14 DNU P14 DNU
Index Location
D-VSS P2 DNU
D-VCC
D-A5
D-A8
D-CAS#
D-CLK#
D-BA1
D-A11
D-A2
RFU
RFU
F-VCC P13 DNU
P3 NC
P4 D-A4
P5 D-A7
P6 D-RAS#
P7 D-CLK
P8 D-VCC
P9 D-BA0
P10 D-A0
P11 D-VCC
P12 D-VSS
Figure 2.2.
133-ball Fine-Pitch Ball Grid Array, 512 Mb Flash + 128 Mb DDR DRAM
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
5
Advance
Information
2.3
512 Mb Flash + 256 Mb DDR SDRAM Pinout
Legend
A1 DNU
A2 D-TEST
A3 D-VSSQ
A4 D-VCCQ
A5 D-DQ9
A6 D-DQ8
A7 D-VSS
A8 D-VCC
A9 D-VCC
A10 D-DQ5
A11 D-DQ3
A12 D-VSSQ
A13 DNU
A14 DNU
Do Not Use
B1 DNU B2 D-VSS B3 D-DQ13 B4 D-UDQS B5 D-DQ10 B6 D-VSSQ B7 D-VCCQ B8 D-VCCQ B9 D-LDQM B10 D-DQ6 B11 D-DQ4 B12 D-DQ1 B13 D-VCCQ B14 DNU
C1 D-VCC
C2 D-DQ15
C3 D-DQ14
C4 D-DQ12
C5 D-DQ11
C6 D-UDQM
C7 D-VSS
C8 D-VCC
C9 D-VSSQ
C10 D-DQ7
C11 D-LDQS
C12 D-DQ2
C13 D-DQ0
C14 D-VSS
Flash Shared
D1 RFU
D2 NC
D3 NC
D4 INDEX
D12 F-OE#
D13 ADQ8
D14 D-VCC
E1 RFU
E2 A22
E3 A17
E12 ADQ9
E13 ADQ1
E14 ADQ0
Flash 1 Only
F1 A23
F2 A19
F3 A18
F12 F-VSS
F13 ADQ3
F14 ADQ2
Flash 2 Only
G1
G2
G3
G12
G13
G14
F1-CE#
F-WP#
F-WE#
F-VCCQ
ADQ11
ADQ10
H1
H2
H3
H12
H13
H14
DRAM Only
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1 A16
J2 F-VSS
J3 NC
J12 F-VSS
J13 F-VSS
J14 ADQ5
Reserved for Future Use
K1 A21
K2 F-AVD#
K3 NC
K12 NC
K13 ADQ7
K14 ADQ6
L1 A20
L2 F-RST#
L3 D-CE#
L12 F-VCCQ
LA13 ADQ15
L14
No Connect
ADQ14 M1 NC M2 NC M3 D-A3 M4 D-A6 M5 D-A9 M6 D-CKE M7 D-VSS M8 D-WE# M9 D-A10 M10 D-A1 M11 RFU M12 F2-CE# M13 F-RDY M14 F-VSS
N1 DNU P1 DNU
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14 DNU P14 DNU
Index Location
D-VSS P2 DNU
D-VCC
D-A5
D-A8
D-CAS#
D-CLK#
D-BA1
D-A11
D-A2
D-A12
RFU
F-VCC P13 DNU
P3 NC
P4 D-A4
P5 D-A7
P6 D-RAS#
P7 D-CLK
P8 D-VCC
P9 D-BA0
P10 D-A0
P11 D-VCC
P12 D-VSS
Figure 2.3.
133-ball Fine-Pitch Ball Grid Array, 512 Mb Flash + 256 Mb DDR DRAM
6
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
Advance
Information
2.4
128 Mb Flash + 128 Mb DDR SDRAM Pinout
Legend
A1 DNU
A2 D-TEST
A3 D-VSSQ
A4 D-VCCQ
A5 D-DQ9
A6 D-DQ8
A7 D-VSS
A8 D-VCC
A9 D-VCC
A10 D-DQ5
A11 D-DQ3
A12 D-VSSQ
A13 DNU
A14 DNU
Do Not Use
B1 DNU B2 D-VSS B3 D-DQ13 B4 D-UDQS B5 D-DQ10 B6 D-VSSQ B7 D-VCCQ B8 D-VCCQ B9 D-LDQM B10 D-DQ6 B11 D-DQ4 B12 D-DQ1 B13 D-VCCQ B14 DNU
C1 D-VCC
C2 D-DQ15
C3 D-DQ14
C4 D-DQ12
C5 D-DQ11
C6 D-UDQM
C7 D-VSS
C8 D-VCC
C9 D-VSSQ
C10 D-DQ7
C11 D-LDQS
C12 D-DQ2
C13 D-DQ0
C14 D-VSS
Code Flash Only
D1 RFU
D2 NC
D3 NC
D4 INDEX
D12 F-OE#
D13 ADQ8
D14 D-VCC
E1 RFU
E2 A22
E3 A17
E12 ADQ9
E13 ADQ1
E14 ADQ0
DRAM Only
F1 NC
F2 A19
F3 A18
F12 F-VSS
F13 ADQ3
F14 ADQ2
G1
G2
G3
G12
G13
G14
Reserved for Future Use
F-CE#
F-WP#
F-WE#
F-VCCQ
ADQ11
ADQ10
H1
H2
H3
H12
H13
H14
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
No Connect
J1 A16
J2 F-VSS
J3 NC
J12 F-VSS
J13 F-VSS
J14 ADQ5
K1 A21
K2 F-AVD#
K3 NC
K12 NC
K13 ADQ7
K14 ADQ6
Index Location
L1 A20
L2 F-RST#
L3 D-CE#
L12 F-VCCQ
LA13 ADQ15
L14 ADQ14
M1 NC
M2 NC
M3 D-A3
M4 D-A6
M5 D-A9
M6 D-CKE
M7 D-VSS
M8 D-WE#
M9 D-A10
M10 D-A1
M11 RFU
M12 NC
M13 F-RDY
M14 F-VSS
N1 DNU P1 DNU
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14 DNU P14 DNU
D-VSS P2 DNU
D-VCC
D-A5
D-A8
D-CAS#
D-CLK#
D-BA1
D-A11
D-A2
RFU
RFU
F-VCC P13 DNU
P3 NC
P4 D-A4
P5 D-A7
P6 D-RAS#
P7 D-CLK
P8 D-VCC
P9 D-BA0
P10 D-A0
P11 D-VCC
P12 D-VSS
Figure 2.4.
133-ball Fine-Pitch Ball Grid Array, 128 Mb Flash + 128 Mb DDR DRAM
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
7
Advance
Information
3
Input/Output Descriptions
A23 - A0 DQ15 - DQ0 F-CE# F-OE# F-WE# F-VCC F-VCCQ F-VSS F-RDY F-CLK = = = = = = = = = = Flash Address inputs Flash Data input/output Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode Flash Output Enable input. Asynchronous relative to CLK for Burst mode. Flash Write Enable input Flash device power supply (1.7 V to 1.95 V) Flash Input/Output Buffer power supply Flash Ground Flash ready output. Indicates the status of the Burst read. VOL = data invalid. VOH = data valid. Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs Flash hardware reset input. VIL= device resets and returns to reading array data Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. DRAM Address inputs. DRAM Data input/output DRAM System Clock DRAM Chip Select DRAM Clock Enable DRAM Bank Select DRAM Row Address Strobe DRAM Column Address Strobe DRAM Data Input/Output Mask DRAM Write Enable input DRAM Ground DRAM Input/Output Buffer ground DRAM Input/Output Buffer power supply DRAM device power supply DRAM Upper Data Strobe, output with read data and input with write data DRAM Lower Data Strobe, output with read data and input with write data DDR Clock for negative edge of CLK Reserved for Future Use No Connect. Can be connected to ground or left floating. Internal Test mode pin for DDR DRAM only. Do not apply any signal on this pin. Can be connected to ground or left floating.
F-AVD#
=
F-RST# F-WP# F-VPP
= = =
D-A11 - D-A0 D-DQ15 - D-DQ0 D-CLK D-CE# D-CKE D-BA1 - BA0 D-RAS# D-CAS# D-DM1 - D-DM0 D-WE# D-VSS D-VSSQ D-VCCQ D-VCC D-UDQS D-LDQS D-CLK# RFU NC D-TEST
= = = = = = = = = = = = = = = = = = = =
8
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
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Information
4
Ordering Information
The order number (Valid Combination) is formed by the following:
S72NS
256
N
D0
AF
W
7
K
0
PACKING TYPE
0 2 3 K J 3 2 7 1 W AF AJ ZJ
= Tray = 7-inch Tape and Reel = 13-inch Tape and Reel = = = = DRAM DRAM DRAM DRAM Type Type Type Type 1, 1, 5, 5, 66 80 66 80 MHz MHz MHz MHz Flash/133 Flash/133 Flash/133 Flash/133 MHz MHz MHz MHz DRAM DRAM DRAM DRAM
MODEL NUMBER
PACKAGE MODIFIER
= DDR DRAM, 133-ball, 11x10 mm, FBGA Multi-chip Package = DDR DRAM, 133-ball, 8.0x8.0 mm, FBGA Multi-chip Package = Wireless (-25C to +85C) = Thin profile Fine-pitch BGA Pb-free package (0.5 mm pitch, 1.0 mm height) = Thin profile Fine-pitch BGA Pb-free LF35 package (0.5 mm pitch, 1.0 mm height) = Thin profile Fine-pitch BGA Pb-free LF35 package (0.5 mm pitch, 1.2 mm height) = 128 Mb DRAM, No Data Flash = 256 Mb DRAM, No Data Flash = 110 nm, MirrorBitTM Technology = 512 Mb = 256 Mb = 128 Mb
TEMPERATURE RANGE
PACKAGE TYPE
DRAM AND DATA FLASH DENSITY
D0 E0 N 512 256 128
PROCESS TECHNOLOGY
CODE FLASH DENSITY
PRODUCT FAMILY
S72NS Multi-Chip Product (MCP) 1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus
Valid Combinations Product Family S72NS Code Flash Density (Mb) 128 256 512 N Process Technology DRAM Density (Mb) D0 E0 Package Type/ Marking/ Material AF, AJ ZJ Temperature Range W Package Modifier 1 7 K, J, 2, 3 0, 2, 3 Model Number Packing Type
Notes:
1. 2. Packing Type 0 is standard. Specify other options as required. BGA package marking omits leading "S" and packing type designator from ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
9
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Information
5
5.1
Physical Dimensions
NLC133--133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 x 1.0 mm MCP Package
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 NLC 133 N/A 11.0 mm x 10.00 mm PACKAGE MIN 0.90 0.20 0.70 10.9 9.9 NOM 1.00 0.25 0.76 11.0 10.0 6.50 BSC. 6.50 BSC. 14 14 133 0.30 0.50 BSC. 0.50 BSC 0.25 BSC. D5-D11, E4-E11, F4-F11 G4-G11, H4-H11, J4-J11 K4-K11, L4-L11 0.35 MAX 1.10 0.30 0.82 11.1 10.1 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3436 \ 16-039.22 \ 12.09.04
10
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
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Information
5.2
NLE133--133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 x 1.0 mm MCP Package
D
1.00 +0.20 -0.50
A1 ID.
A
D1 eD eE
14 13 12 11 10 9 8 7 6 5 432 1 A B C D E F G H J K L M N P
A1 CORNER
0.10 C
0.50 REF
+0.20 -0.50
0.50 REF
1.00
7
SE E1
E
B
0.10 C
6
b
SD
7
0.08 M C 0.15 M C A B
TOP VIEW
A
A1 A2
0.10 C
BOTTOM VIEW
SEATING PLANE
C
0.08 C
SIDE VIEW
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 NLE 133 N/A 8.00 mm x 8.00 mm PACKAGE MIN 0.90 0.20 0.70 7.90 7.90 NOM 1.00 0.25 0.76 8.00 8.00 6.50 BSC. 6.50 BSC. 14 14 133 0.30 0.50 BSC. 0.50 BSC 0.25 BSC. 0.35 MAX 1.10 0.30 0.82 8.10 8.10 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 8. 9 6 7 4. 5. NOTE 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1 SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3513 \ 16-038.22 \ 08.09.05
D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS H4-H11,J4-J11,K4-K11,L4-L11
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
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Information
5.3
MTA133--133-ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 11.0 x 1.0 mm MCP Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
PIN A1 CORNER
A B C D E F G H J K
SE 7 E1
E eE
0.10 C (2X)
14 13 12 11 10 9 8 7654 3 21
L M N P
B
SD BOTTOM VIEW
0.10 C
7
TOP VIEW
0.10 C (2X)
A A2 A1
6
C
0.08 C
SIDE VIEW b
M CAB MC
133X
0.15 0.08
NOTES: PACKAGE JEDEC DXE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SE SD 0.25 MTA 133 N/A 11.00 mm x 10.00 mm PACKAGE MIN --0.20 0.91 NOM ------11.00 BSC. 10.00 BSC. 6.50 BSC. 6.50 BSC. 14 14 133 133 2 0.30 0.50 BSC. 0.50 BSC 0.25 BSC. 4L ~ 4E, 5L ~ 5D, 6L ~ 6D, 7L ~ 7D, 8L ~ 8D, 9L ~ 9D, 10L ~ 10D, 11L ~ 11D 0.35 MAX 1.30 --1.06 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PERIMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALL 8. 9 7 6 NOTE 4. 5. 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE CROWNS OF THE SOLDER BALLS. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3529 / 16.038 / 11.08.05
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
12
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
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Information
6
Revision Summary
MCP Revision History
Revision A0 (January 3, 2005)
Initial release.
Revision A1 (April 25, 2005)
Global Updated the flash module Updated the SDRAM Type 1 module
Revision A2 (May 20, 2005)
Global Data sheet format modularized. Distinctive Characteristics Package description changed from 10.0 x 11.0 x 1.0 to 11.0 x 10.0 x 1.0 MCP Block Diagrams Changed the F-ACC signal to F-VPP Changed the ACC description to VPP Connection Diagrams Changed the F-ACC pin to F-VPP Input/Output Descriptions Updated description for F-RDY Changed the F-ACC description to F-VPP Updated description for NC and D-TEST Product Revision Identification New section added.
Revision B0 (August 15, 2005)
Global Data sheet revised to include 128/128 MCP details. Distinctive Characteristics Package description changed to include new 128/128 MCP details and update the Product Selector Guide table. Connection Diagrams New 128 Mb Flash + 128 Mb DDR SDRAM Pinout added. Ordering Information New valid combinations added to the table. Physical Dimensions New illustration for 8.0 x 8.0 x 1.0 mm MCP Package added.
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
13
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Information
Revision B1 (November 9, 2005)
Added DDR DRAM Type 5 Information Updated General Description, Product Selector Guide, Ordering Information, and Valid Combinations with DDR DRAM Type 5 Information. S29NS-N Flash Module Removed all of the Revision Summary except for A4 (request from customer). SDRAM (Micron) Revision Summary Removed all of the Revision Summary except for A1 (request from customer). SDRAM (Elpida) Revision Summary New SDRAM to be added to MCP
S29NS-N Revision Summary
Revision A4 Flash Module (April 21, 2005)
Global Changes Removed all ordering options and package information listed in revision A4 of the discrete data sheet. Removed 54 MHz speed option. Changed ACC to VPP. Read Access Times Removed burst access for 54MHz. Defined asynchronous random access and synchronous random access to 80 ns for all speed options. DC Characteristics CMOS Compatible Table. Updated ICC3 and ICC6 values from 40 A to 70 A.
SDRAM Type 1 Revision Summary
Revision A2 (November 1, 2005)
Features Changed VDD/VDDQ range from 1.7 V-1.9 V to 1.7 V-1.95 V Indicated temperature range (-40C to 85C) Stopping the External Clock Removed information that limited the rate of frequency change. IDD Specifications and Conditions table Specifications and conditions updated. Electrical Characteristics and Recommended AC Operating Conditions table Removed tREFC parameter
SDRAM Type 5 Revision Summary
Revision A0 (September 30, 2005)
Initial release. New SDRAM module.
14
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
Advance
Information
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2005 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
15

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